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ad7564 a features four 12-bit dacs in one package 4-quadrant multiplication separate references single supply operation guaranteed specifications with +3.3 v/+5 v supply low power versatile serial interface simultaneous update capability reset function 28-pin soic, ssop and dip packages applications process control portable instrumentation general purpose test equipment functional block diagram v a r b dac a dac a latch input latch a input latch b input latch c input latch d dac b latch dac c latch dac d latch dac b dac c dac d v b ref v d ref r d r c fb fb r a fb ref v c ref v dd dgnd ldac clr ad7564 12 12 12 12 12 12 12 control logic + input shift register clkin sdin sdout 12 fsin i a i a i b i b i c i d out1 out2 out1 out2 out1 fb out1 a0 a1 12 nc agnd i c out2 i d out2 product highlights 1. the ad7564 contains four 12-bit current output dacs with separate v ref inputs. 2. the ad7564 can be operated from a single +3.3 v to +5 v supply. 3. simultaneous update capability and reset function are available. 4. the ad7564 features a fast, versatile serial interface com- patible with modern 3 v and 5 v microprocessors and microcomputers. 5. low power, 50 m w at 5 v and 33 m w at 3.3 v. lc 2 mos +3.3 v/+5 v, low power, quad 12-bit dac one technology way, p.o. box 9106, norwood. ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. general description the ad7564 contains four 12-bit dacs in one monolithic device. the dacs are standard current output with separate v ref , i out1 , i out2 and r fb terminals. these dacs operate from a single +3.3 v to +5 v supply. the ad7564 is a serial input device. data is loaded using fsin , clkin and sdin. two address pins a0 and a1 set up a device address, and this feature may be used to simplify device loading in a multi-dac environment. alternatively, a0 and a1 can be ignored and the serial out capability used to configure a daisy-chained system. all dacs can be simultaneously updated using the asynchro- nous ldac input, and they can be cleared by asserting the asynchronous clr input. the device is packaged in 28-pin soic, ssop and dip packages.
parameter b grade 1 units test conditions/comments accuracy resolution 12 bits 1 lsb = v ref /2 12 = 2.44 mv when v ref = 10 v relative accuracy 0.5 lsb max differential nonlinearity 0.5 lsb max all grades guaranteed monotonic over temperature gain error +25 c 4 lsbs max t min to t max 5 lsbs max gain temperature coefficient 2 2 ppm fsr/ c typ 5 ppm fsr/ c max output leakage current i out1 @ +25 c 10 na max t min to t max 50 na max reference input input resistance 6 k w min typical input resistance = 9.5 k w 13 k w max ladder resistance mismatch 2 % max typically 0.6% digital inputs v inh , input high voltage 2.4 v min v inl , input low voltage 0.8 v max i inh , input current 1 m a max c in , input capacitance 2 10 pf max digital output (sdout) output low voltage (v ol ) 0.4 v max load circuit as in figure 2. output high voltage (v oh ) 4.0 v min power requirements v dd range 4.75/5.25 v min/v max part functions from 3.3 v to 5.25 v power supply rejection 2 d gain/ d v dd C75 db typ i dd 10 m a max v inh = v dd , v inl = 0 v at input levels of 0.8 v and 2.4 v, i dd is typically 2 ma. notes 1 temperature range is as follows: b version: C40 c to +85 c. 2 not production tested. guaranteed by characterization at initial product release. specifications subject to change without notice. rev. a normal mode ad7564Cspecifications (v dd = +4.75 v to +5.25 v; i out1 a to i out1 d = i out2 a = i out2 d = agnd = 0 v; v ref = +10 v; t a = t min to t max , unless otherwise noted) C2C
parameter a grade 2 units test conditions/comments accuracy resolution 12 bits 1 lsb = (v iout2 C v ref )/2 12 = 300 m v when v iout2 = 1.23 v and v ref = 0 v relative accuracy 1 lsb max differential nonlinearity 0.9 lsb max all grades guaranteed monotonic over temperature gain error +25 c 4 lsbs max t min to t max 5 lsbs max gain temperature coefficient 3 2 ppm fsr/ c typ 5 ppm fsr/ c max output leakage current see terminology section i out1 @ +25 c 10 na max t min to t max 50 na max input resistance @ i out2 pins 6 k w min this varies with dac input code digital inputs v inh , input high voltage @ v dd = +5 v 2.4 v min v inh , input high voltage @ v dd = +3.3 v 2.1 v min v inl , input low voltage @ v dd = +5 v 0.8 v max v inl , input low voltage @ v dd = +3.3 v 0.6 v max i inh , input current 1 m a max c in , input capacitance 3 10 pf max digital output (sdout) load circuit as in figure 2. output low voltage (v ol ) 0.4 v max v dd = +5 v output low voltage (v ol ) 0.2 v max v dd = +3.3 v output high voltage (v oh ) 4.0 v min v dd = +5 v output high voltage (v oh )v dd C 0.2 v min v dd = +3.3 v power requirements v dd range 3/5.5 v min/v max power supply sensitivity 3 d gain/ d v dd C75 db typ i dd 10 m a max v inh = v dd C 0.1 v min, v inl = 0.1 v max; sdout open circuit i dd is typically 2 ma with v dd = +5 v, v inh = 2.4 v min, v inl = 0.8 v max; sdout open circuit notes 1 these specifications apply with the devices biased up at 1.23 v for single supply applications. the model numbering reflects this by means of a "-b" suffix (for example: ad7564ar-b). figure 19 is an example of biased mode operation. 2 temperature ranges is as follows: a version: C40 c to +85 c. 3 not production tested. guaranteed by characterization at initial product release. specifications subject to change without notice. biased mode 1 (v dd = +3 v to +5.5 v; v iout1 = v iout2 = 1.23 v; agnd = 0 v; v ref = 0 v to 2.45 v; t a = t min to t max , unless otherwise noted) C3C rev. a ad7564
rev. a ad7564 C4C parameter a grade units test conditions/comments dynamic performance output voltage settling time 3.5 m s typ to 0.01% of full-scale range. v ref = 0 v. dac latch alter- nately loaded with all 0s and all 1s. digital to analog glitch impulse 35 nv-s typ measured with v iout2 = 0 v and v ref = 0 v. dac register alter- nately loaded with all 0s and all 1s. multiplying feedthrough error C70 db max dac latch loaded with all 0s. output capacitance 100 pf max all 1s loaded to dac 40 pf max all 0s loaded to dac digital feedthrough 5 nv-s typ feedthrough to any dac output with fsin high and a square wave applied to sdin and clkin total harmonic distortion C76 db typ output noise spectral density @ 1 khz 20 nv/ ? hz typ all 1s loaded to dac. v iout2 = 0 v; v ref = 0 v (v dd = +3 v to +5.5 v; v iout1 = v iout2 = 1.23 v; agnd = 0 v. v ref = 1 khz, 2.45 v p-p, sine wave biased at 1.23 v; dac output op amp is ad820; t a = t min to t max , unless otherwise noted. these characteristics are included for design guidance and are not subject to test.) biased mode ac performance characteristics parameter b grade units test conditions/comments dynamic performance output voltage settling time 550 ns typ to 0.01% of full-scale range. dac latch alternately loaded with all 0s and all 1s digital-to-analog glitch impulse 35 nv-s typ measured with v ref = 0 v. dac register alternately loaded with all 0s and all 1s multiplying feedthrough error C70 db max v ref = 20 v p-p, 10 khz sine wave. dac latch loaded with all 0s output capacitance 60 pf max all 1s loaded to dac 30 pf max all 0s loaded to dac channel-to-channel isolation C76 db typ feedthrough from any one reference to the others with 20 v p-p, 10 khz sine wave applied digital crosstalk 5 nv-s typ effect of all 0s to all 1s code transition on nonselected dacs digital feedthrough 5 nv-s typ feedthrough to any dac output with fsin high and square wave applied to sdin and sclk total harmonic distortion C83 db typ v ref = 6 v rms, 1 khz sine wave output noise spectral density @ 1 khz 30 nv/ ? hz typ all 1s loaded to the dac. v ref = 0 v. output op amp is adop07 normal mode (v dd = +4.75 v to +5.25 v; v iout1 = v iout2 = agnd = 0 v. v ref = 6 v rms, 1 khz sine wave; dac output op amp is ad843; t a = t min to t max , unless otherwise noted. these characteristics are included for design guidance and are not subject to test.) ac performance characteristics
C5C rev. a 3 ad7564 timing specifications 1 (t a = t min to t max unless otherwise noted) limit at limit at parameter v dd = +3 v to +3.6 v v dd = +4.75 v to +5.25 v units description t 1 180 100 ns min clkin cycle time t 2 80 40 ns min clkin high time t 3 80 40 ns min clkin low time t 4 50 30 ns min fsin setup time t 5 50 30 ns min data setup time t 6 10 5 ns min data hold time t 7 125 90 ns min fsin hold time t 8 2 100 70 ns max sdout valid after clkin falling edge t 9 80 40 ns min ldac , clr pulse width notes 1 not production tested. guaranteed by characterization at initial product release. all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v for a v dd of 5 v and from a voltage level 1.35 v for a v dd of 3.3 v. 2 t 8 is measured with the load circuit of figure 2 and defined as the time required for the output to cross 0.8 v or 2.4 v with a v dd of 5 v and 0.6 v or 2.1 v for a v dd of 3.3 v. db15 db15 db0 t 2 t 3 t 4 t 5 t 7 t 8 t 9 db0 t 6 t 1 fsin(i) clkin(i) sdin(i) sdout(o) ldac, clr figure 1. timing diagram 1.6ma +1.6v 200? c l 50pf to output pin i ol i oh figure 2. load circuit for digital output timing specifications
rev. a ad7564 C6C absolute maximum ratings 1 (t a = +25 c unless otherwise noted) v dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +6 v i out1 to dgnd . . . . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v i out2 to dgnd . . . . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v agnd to dgnd . . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v digital input voltage to dgnd . . . . . . C0.3 v to v dd + 0.3 v v rfb , v ref to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 v input current to any pin except supplies 2 . . . . . . . . 10 ma operating temperature range commercial plastic (a, b versions). . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150 c dip package, power dissipation . . . . . . . . . . . . . . . . . 875 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . 75 c/w lead temperature, soldering (10 sec) . . . . . . . . . . 260 c soic package, power dissipation . . . . . . . . . . . . . . . . 875 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . 75 c/w lead temperature, soldering (10 sec) . . . . . . . . . . 260 c vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . +220 c ssop package, power dissipation . . . . . . . . . . . . . . . . 900 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . 100 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . +220 c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch-up. pin configuration dip, soic and ssop packages nc = no connect dgnd i out2 c i out2 b agnd r fb c v ref c i out2 d r fb b v ref b i out2 a v dd i out1 c nc i out1 b i out1 d i out1 a r fb d r fb a v ref d v ref a sdout a0 clr a1 ldac o clkin fsin sdin 13 18 1 2 28 27 5 6 7 24 23 22 3 4 26 25 821 920 10 19 11 11 12 17 16 14 15 top view (not to scale) ad7564 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7564 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device ordering guide temperature linearity nominal package model range error (lsbs) supply voltage option* ad7564bn C40 c to +85 c 0.5 +5 v n-28 ad7564br C40 c to +85 c 0.5 +5 v r-28 AD7564BRS C40 c to +85 c 0.5 +5 v rs-28 ad7564ar-b C40 c to +85 c 1 +3.3 v to +5 v r-28 ad7564ars-b C40 c to +85 c 1 +3.3 v to +5 v rs-28 *n = dip; r = soic; rs = ssop.
C7C rev. a 3 ad7564 pin descriptions pin number mnemonic description 1 dgnd digital ground. 2i out2 ci out2 terminal for dac c. this should normally connect to the signal ground of the system. 3v dd positive power supply. this is +5 v 5%. 4i out1 ci out1 terminal for dac c. 5r fb c feedback resistor for dac c. 6v ref c dac c reference input. 7i out2 di out2 terminal for dac d. this should normally connect to the signal ground of the system. 8i out1 di out1 terminal for dac d. 9r fb d feedback resistor for dac d. 10 v ref d dac d reference input. 11 sdout this shift register output allows multiple devices to be connected in a daisy chain configuration. 12 clr asynchronous clr input. when this input is taken low, all dac latches are loaded with all 0s. 13 ldac asynchronous ldac input. when this input is taken low, all dac latches are simultaneously updated with the contents of the input latches. 14 fsin level-triggered control input (active low). this is the frame synchronization signal for the input data. when fsin goes low, it enables the input shift register, and data is transferred on the falling edges of clkin. if the address bits are valid, the 12-bit dac data is transferred to the appropriate input latch on the sixteenth falling edge after fsin goes low. 15 sdin serial data input. the device accepts a 16-bit word. db0 and db1 are dac select bits. db2 and db3 are device address bits. db4 to db15 contain the 12-bit data to be loaded to the selected dac. 16 clkin clock input. data is clocked into the input shift register on the falling edges of clkin. 17 a1 device address pin. this input in association with a0 gives the device an address. if db2 and db3 of the serial input stream do not correspond to this address, the data which follows is ignored and not loaded to any input latch. however, it will appear at sdout irrespective of this. 18 a0 device address pin. this input in association with a1 gives the device an address. 19 v ref a dac a reference input. 20 r fb a feedback resistor for dac a. 21 i out1 ai out1 terminal for dac a. 22 i out2 ai out2 terminal for dac a. this should normally connect to the signal ground of the system. 23 v ref b dac b reference input. 24 r fb b feedback resistor for dac b. 25 i out1 bi out1 terminal for dac b. 26 n/c no connect pin. 27 agnd this pin connects to the back gates of the current steering switches. it should be connected to the signal ground of the system. 28 i out2 bi out2 terminal for dac b. this should normally connect to the signal ground of the system.
rev. a ad7564 C8C table ii. dac selection ds1 ds0 function 0 0 dac a selected 0 1 dac b selected 1 0 dac c selected 1 1 dac d selected output voltage settling time this is the amount of time it takes for the output to settle to a specified level for a full-scale input change. for the ad7564, it is specified with the ad843 as the output op amp. digital to analog glitch impulse this is the amount of charge injected into the analog output when the inputs change state. it is normally specified as the area of the glitch in either pa-secs or nv-secs, depending upon whether the glitch is measured as a current or voltage signal. it is measured with the reference input connected to agnd and the digital inputs toggled between all 1s and all 0s. ac feedthrough error this is the error due to capacitive feedthrough from the dac reference input to the dac i out terminal, when all 0s are loaded in the dac. channel-to-channel isolation channel-to-channel isolation refers to the proportion of input signal from one dacs reference input which appears at the output of any other dac in the device and is expressed in dbs. digital crosstalk the glitch impulse transferred to the output of one converter due to a change in digital input code to the other converter is defined as the digital crosstalk and is specified in nv-secs. digital feedthrough when the device is not selected, high frequency logic activity on the device digital inputs is capacitively coupled through the de- vice to show up at on the i out pin and subsequently on the op amp output. this noise is digital feedthrough. terminology relative accuracy relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is measured after ad- justing for zero error and full-scale error and is normally ex- pressed in least significant bits or as a percentage of full-scale reading. differential nonlinearity differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. gain error gain error is a measure of the output error between an ideal dac and the actual device output. it is measured with all 1s in the dac after offset error has been adjusted out and is ex- pressed in least significant bits. gain error is adjustable to zero with an external potentiometer. output leakage current output leakage current is current which flows in the dac ladder switches when these are turned off. for the i out1 terminal, it can be measured by loading all 0s to the dac and be measured by loading all 0s to the dac and measuring the i out1 current. minimum current will flow in the i out2 line when the dac is loaded with all 1s. this is a combination of the switch leakage current and the ladder termination resistor current. the i out2 leakage current is typically equal to that in i out1 . output capacitance this is the capacitance from the i out1 pin to agnd. table i. ad7564 loading sequence db15 db0 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 a1 a0 ds1 ds0
C9C rev. a 0.5 0.0 10 0.3 0.1 4 0.2 2 0.4 8 6 v ref ?volts dnl ?lsbs normal mode of operation v dd = +5v t a = +25 c figure 3. differential nonlinearity error vs. v ref (normal mode) 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 10 3 10 4 10 6 10 5 frequency ?hz v out b/v out c ?dbs v ref c = 20v p-p sine wave all other reference inputs = 0v dac c loaded with all 1s all other dacs loaded with all 0s figure 4. channel-to-channel isolation (1 dac to 1 dac) ?0 ?00 ?0 ?0 ?0 ?0 10 2 10 3 10 5 10 4 frequency ?hz thd ?dbs normal mode of operation v dd = +5v v in = +6v rms op amp = ad713 t a = +25 c figure 5. total harmonic distortion vs. frequency (normal mode) 0.5 0.0 10 0.3 0.1 4 0.2 2 0.4 8 6 v ref ?volts inl ?lsbs normal mode of operation v dd = +5v t a = +25 c figure 6. integral nonlinearity error vs. v ref (normal mode) 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 10 3 10 4 10 6 10 5 frequency ?hz v out b/v out c ?dbs v ref b = 0v all other reference inputs = 20v p-p sine wave dac b loaded with all 0s all other dacs loaded with all 1s figure 7. channel-to-channel isolation (1 dac to all other dacs) frequency ?hz 0 ?0 ?0 1k ?0 ?0 ?0 v dd = +5v t a = +25 c v in = 20v p-p op amp = ad711 gain ?db dac loaded with all 1s dac loaded with all 0s ?0 ?0 ?0 ?0 ?00 10k 100k 1m 10m figure 8. multiplying frequency response vs. digital code (normal mode) typical performance curvesCad7564
rev. a ad7564 C10C 2.0 0.0 1.4 0.6 0.2 0.4 0.4 0.2 1.2 0.8 1.0 1.4 1.6 1.8 1.2 1.0 0.8 0.6 |v ref ?v bias | ?volts inl ?lsbs v dd = +3.3v t a = +25 c op amp = ad820 v ref = +1.23v (ad589) figure 9. integral nonlinearity error vs. v ref (biased mode) 2.0 0.0 1.4 0.6 0.2 0.4 0.4 0.2 1.2 0.8 1.0 1.4 1.6 1.8 1.2 1.0 0.8 0.6 |v ref ?v bias | ?volts v dd = +5v t a = +25 c op amp = ad820 v bias = +1.23v (ad589) inl ?lsbs figure 10. integral nonlinearity error vs. v ref (biased mode) 0.2 ?.5 4095 ?.2 ?.4 1024 ?.3 0 0.1 ?.1 0.0 3072 2048 code ?lsbs linearity error ?lsbs v dd = +3.3v t a = +25 c v bias = 1.23v v ref = 0v figure 11. all codes linearity plot (biased mode) 2.0 0.0 1.4 0.6 0.2 0.4 0.4 0.2 1.2 0.8 1.0 1.4 1.6 1.8 1.2 1.0 0.8 0.6 |v ref ?v bias | ?volts dnl ?lsbs v dd = +3.3v t a = +25 c op amp = ad820 v ref = +1.23v (ad589) figure 12. differential nonlinearity error vs. v ref (biased mode) 2.0 0.0 1.4 0.6 0.2 0.4 0.4 0.2 1.2 0.8 1.0 1.4 1.6 1.8 1.2 1.0 0.8 0.6 |v ref ?v bias | ?volts dnl ?lsbs v dd = +5v t a = +25 c op amp = ad820 v bias = +1.23v (ad589) figure 13. differential nonlinearity error vs. v ref (biased mode) linearity error ?lsbs 0.4 ?.1 0.2 0.0 0.1 0.3 4095 1024 0 3072 2048 code ?lsbs normal mode v dd = +5v t a = +25 c v ref = 10v figure 14. all codes linearity plot (normal mode)
C11C rev. a 3 ad7564 general description d/a section the ad7564 contains four 12-bit current output d/a convert- ers. a simplified circuit diagram for one of the d/a converters is shown in figure 15. v ref 2r 2r 2r 2r 2r 2r 2r cba s9 s8 s0 r fb i out1 i out2 r r r r/2 shown for all 1s on dac figure 15. simplified d/a circuit diagram a segmented scheme is used whereby the 2 msbs of the 12-bit data word are decoded to drive the three switches a, b and c. the remaining 10 bits of the data word drive the switches s0 to s9 in a standard r-2r ladder configuration. each of the switches a to c steers 1/4 of the total reference current with the remaining current passing through the r-2r section. all dacs have separate v ref , i out1 , i out2 and r fb pins. when an output amplifier is connected in the standard configu- ration of figure 17, the output voltage is given by: v out = d v ref where d is the fractional representation of the digital word loaded to the dac. thus, in the ad7564, d can be set from 0 to 4095/4096. interface section the ad7564 is a serial input device. three input signals con- trol the serial interface. these are fsin , clkin and sdin. the timing diagram is shown in figure 1. data applied to the sdin pin is clocked into the input shift reg- ister on each falling edge of clkin. sdout is the shift regis- ter output. it allows multiple devices to be connected in a daisy chain fashion with the sdout pin of one device connected to the sdin of the next device. fsin is the frame synchronization for the device. when the sixteen bits have been received in the input shift regis- ter, db2 and db3 (a0 and a1) are checked to see if they corre- spond to the state on pins a0 and a1. if it does, then the word is accepted. otherwise, it is disregarded. this allows the user to address a number of ad7564s in a very simple fashion. db1 and db0 of the 16-bit word determine which of the four dac input latches is to be loaded. when the ldac line goes low, all four dac latches in the device are simultaneously loaded with the contents of their respective input latches and the outputs change accordingly. bringing the clr line low resets the dac latches to all 0s. the input latches are not affected so that the user can revert to the previous analog output if desired. 16-bit input shift register clkin fsin sdin sdout figure 16. input logic unipolar binary operation (2-quadrant multiplication) figure 17 shows the standard unipolar binary connection dia- gram for one of the dacs in the ad7564. when v in is an ac signal, the circuit performs 2-quadrant multiplication. resistors r1 and r2 allow the user to adjust the dac gain error. offset can be removed by adjusting the output amplifier offset voltage. figure 17. unipolar binary operation a1 should be chosen to suit the application. for example, the ad707 is ideal for very low bandwidth applications while the ad843 and ad845 offer very fast settling time in wide band- width applications. appropriate multiple versions of these am- plifiers can be used with the ad7564 to reduce board space requirements. the code table for figure 17 is shown in table iii. table iii. unipolar binary code table digital input analog output msb . . . lsb (v out as shown in figure 17) 1111 1111 1111 Cv ref (4095/4096) 1000 0000 0001 Cv ref (2049/4096) 1000 0000 0000 Cv ref (2048/4096) 0111 1111 1111 Cv ref (2047/4096) 0000 0000 0001 Cv ref (1/4096) 0000 0000 0000 Cv ref (0/4096) = 0 note nominal lsb size for the circuit of figure 17 is given by: v ref (1/4096). dac a a1 ad7564 v ref a v in notes 1. only one dac is shown for clarity. 2. digital input connections are omitted. 3. c1 phase compensation (5?5pf) may be required when using high speed amplifier. r2 10 w r1 20 w signal gnd a1: ad707 ad711 ad843 ad845 c1 r fb a i out2 a i out1 a v out
rev. a ad7564 C12C in the current mode circuit of figure 19, i out2 and hence i out1 , is biased positive by an amount v bias . for the circuit to operate correctly, the dac ladder termination resistor must be con- nected internally to i out2 . this is the case with the ad7564. the output voltage is given by: v out = d r fb r dac ( v bias v in ) ? y t + v bias as d varies from 0 to 4095/4096, the output voltage varies from v out = v bias to v out = 2 v bias C v in . v bias should be a low impedance source capable of sinking and sourcing all pos- sible variations in current at the i out2 terminal without any problems. voltage mode circuit figure 20 shows dac a of the ad7564 operating in the voltage-switching mode. the reference voltage, v in is applied to the i out1 pin, i out2 is connected to agnd and the output voltage is available at the v ref terminal. in this configuration, a positive reference voltage results in a positive output voltage; making single supply operation possible. the output from the dac is a voltage at a constant impedance (the dac ladder re- sistance). thus, an op amp is necessary to buffer the output voltage. the reference voltage input no longer sees a constant input impedance, but one which varies with code. so, the volt- age input should be driven from a low impedance source. it is important to note that v in is limited to low voltages be- cause the switches in the dac no longer have the same source- drain voltage. as a result, their on-resistance differs and this degrades the integral linearity of the dac. also, v in must not go negative by more than 0.3 volts or an internal diode will turn on, causing possible damage to the device. this means that the full-range multiplying capability of the dac is lost. a1 v ref a r fb a i out1 a v in v out i out2 a r1 r2 ad7564 dac a 1. only one dac is shown for clarity. 2. digital input connections are omitted. 3. c1 phase compensation (5?5pf) may be required when using high speed amplifier. notes figure 20. single supply voltage switching mode operation bipolar operation 4-quadrant multiplication) figure 18 shows the standard connection diagram for bipolar operation of any one of the dacs in the ad7564. the coding is offset binary as shown in table iv. when v in is an ac signal, the circuit performs 4-quadrant multiplication. to maintain the gain error specifications, resistors r3, r4 and r5 should be ratio matched to 0.01%. a1 dac a ad7564 v ref a v in notes: 1. only one dac is shown for clarity. 2. digital input connections are omitted. 3. c1 phase compensation (5?5pf) may be required when using high speed amplifier, a1. r2 10 w r1 20 w signal gnd c1 r fb a i out1 a v out r4 20k w i out2 a 20k w r5 r4 20 w a2 r3 10k w figure 18. bipolar operation (4-quadrant multiplication) table iv. bipolar (offset binary) code table digital input analog output msb . . . lsb (v out as shown in figure 18) 1111 1111 1111 Cv ref (2047/2048) 1000 0000 0001 Cv ref (1/2048) 1000 0000 0000 Cv ref (0/2048 = 0) 0111 1111 1111 Cv ref (1/2048) 0000 0000 0001 Cv ref (2047/2048) 0000 0000 0000 Cv ref (2048/2048) = Cv ref note nominal lsb size for the circuit of figure 18 is given by: v ref (1/2048). single supply applications the Cb versions of the ad7564 are specified and tested for single supply applications. figure 19 shows a typical circuit for operation with a single +3.3 v to +5 v supply. a1 dac a ad7564 v ref a r fb a i out1 a i out2 a v in v bias v out notes: 1. only one dac is shown for clarity. 2. digital input connections are omitted. 3. c1 phase compensation (5?5pf) may be required when using high speed amplifier, a1. figure 19. single supply current mode operation
C13C rev. a 3 ad7564 microprocessor interfacing ad7564 to 80c51 interface a serial interface between the ad7564 and the 80c51 micro- controller is shown in figure 21. txd of the 80c51 drives sclk of the ad7564 while rxd drives the serial data line of the part. the fsin signal is derived from the port line p3.3. the 80c51 provides the lsb of its sbuf register as the first bit in the serial data stream. therefore, the user will have to ensure that the data in the sbuf register is arranged correctly so that the data word transmitted to the ad7564 corresponds to the loading sequence shown in table i. when data is to be trans- mitted to the part, p3.3 is taken low. data on rxd is valid on the falling edge of txd. the 80c51 transmits its serial data in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. to load data to the ad7564, p3.3 is left low after the first eight bits are transferred and a second byte of data is then transferred serially to the ad7564. when the second serial transfer is complete, the p3.3 line is taken high. note that the 80c51 outputs the serial data byte in a format which has the lsb first. the ad7564 expects the msb first. the 80c51 transmit routine should take this into account. clr fsin sclk sdin ldac p3.5 p3.3 txd rxd p3.4 80c51* ad7564* *additional pins ommitted for clarity figure 21. ad7564 to 80c51 interface ldac and clr on the ad7564 are also controlled by 80c51 port outputs. the user can bring ldac low after every two bytes have been transmitted to update the dac which has been programmed. alternatively, it is possible to wait until all the in- put registers have been loaded (sixteen byte transmits) and then update the dac outputs. ad7564 to 68hc11 interface figure 22 shows a serial interface between the ad7564 and the 68hc11 microcontroller. sck of the 68hc11 drives sclk of the ad7564 while the mosi output drives the serial data line of the ad7564. the fsin signal is derived from a port line (pc7 shown). for correct operation of this interface, the 68hc11 should be configured such that its cpol bit is a 0 and its cpha bit is a 1. when data is to be transmitted to the part, pc7 is taken low. when the 68hc11 is configured like this, data on mosi is valid on the falling edge of sck. the 68hc11 transmits its serial data in 8-bit bytes (msb first), with only eight falling clock edges occurring in the transmit cycle. to load data to the ad7564 , pc7 is left low after the first eight bits are transferred and a second byte of data is then transferred serially to the ad7564. when the second serial transfer is complete, the pc7 line is taken high. clr fsin sclk sdin ldac pc5 pc7 sck mosi pc6 64hc11* ad7564* *additional pins ommitted for clarity figure 22. ad7564 to 64hc11 interface in figure 22, ldac and clr are controlled by the pc6 and pc5 port outputs. as with the 80c51, each dac of the ad7564 can be updated after each two-byte transfer, or else all dacs can be simultaneously updated. this interface is suitable for both 3 v and 5 v versions of the 68hc11 microcontroller.
rev. a ad7564 C14C ad7564 to adsp-2101/adsp-2103 interface figure 23 shows a serial interface between the ad7564 and the adsp-2101/adsp-2103 digital signal processors. the adsp- 2101 operates from 5 v while the adsp-2103 operates from 3 v supplies. these processors are set up to operate in the sport transmit alternate framing mode. the following dsp conditions are recommended: internal sclk; active low framing signal; 16-bit word length. trans- mission is initiated by writing a word to the tx register after the sport has been enabled. the data is then clocked out on ev- ery rising edge of sclk after tfs goes low. tfs stays low un- til the next data transfer. clr fsin sdin clkin ldac tfs dt sclk fo adsp-2101/ adsp-2103 ad7564* *additional pins ommitted for clarity +5v figure 23. ad7564 to adsp-2101/adsp-2103 interface ad7564 to tms320c25 interface figure 24 shows an interface circuit for the tms320c25 digital signal processor. the data on the dx pin is clocked out of the processors transmit shift register by the clkx signal. sixteen-bit transmit format should be chosen by setting the fo bit in the st1 register to 0. the transmit operation begins when data is written into the data transmit register of the tms320c25. this data will be transmitted when the fsx line goes low while clkx is high or going high. the data, starting with the msb, is then shifted out to the dx pin on the rising edge of clkx. when all bits have been transmitted, the user can update the dac outputs by bringing the xf output flag low. clr fsin sdin clkin ldac fsx dx clkx xf tms320c25* ad7564* *additional pins ommitted for clarity +5v clock generation figure 24. ad7564 to tms320c25 interface application hints output offset cmos d/a converters in circuits such as figures 17, 18 and 19 exhibit a code dependent output resistance which in turn can cause a code dependent error voltage at the output of the ampli- fier. the maximum amplitude of this error, which adds to the d/a converter nonlinearity, depends on v os , where v os is the amplifier input offset voltage. for the ad7564 to maintain specified accuracy with v ref at 10 v, it is recommended that v os be no greater than 500 m v, or (50 10 C6 ) (v ref ), over the temperature range of operation. suitable amplifiers include the adop-07, adop-27, ad711, ad845 or multiple versions of these. temperature coefficients the gain temperature coefficient of the ad7564 has a maxi- mum value of 5 ppm/ c and a typical value of 2 ppm/ c. this corresponds to gain shifts of 2 lsbs and 0.8 lsbs respectively over a 100 c temperature range. when trim resistors r1 and r2 are used to adjust full scale in figures 17 and 18, their tem- perature coefficients should be taken into account. for further information see gain error and gain temperature coefficient of cmos multiplying dacs, application note, publication number e630c-5-3/86, available from analog devices. high frequency considerations the output capacitances of the ad7564 dacs work in con- junction with the amplifier feedback resistance to add a pole to the open loop response. this can cause ringing or oscillation. stability can be restored by adding a phase compensation ca- pacitor in parallel with the feedback resistor. this is shown as c1 in figures 17 and 18.
C15C rev. a 3 ad7564 applications programmable state variable filter the ad7564 with its multiplying capability and fast settling time is ideal for many types of signal conditioning applications. the circuit of figure 25 shows its use in a state variable filter design. this type of filter has three outputs: low pass, high pass and bandpass. the particular version shown in figure 25 uses the ad7564 to control the critical parameters f o , q and a o . in- stead of several fixed resistors, the circuit uses the dac equiva- lent resistances as circuit elements. thus, r1 in figure 25 is controlled by the 12-bit digital word loaded to dac a of the ad7564. this is also the case with r2, r3 and r4. the fixed resistor r5 is the feedback resistor, r fb b. dac equivalent resistance, r eq = (r ladder 4 096)/n where: r ladder is the dac ladder resistance n is the dac digital code in decimal (0 < n < 4096) in the circuit of figure 25: c1 = c2, r7 = r8, r3 = r4 (i.e., the same code is loaded to each dac). resonant frequency , f o = 1/(2 p r 3 c 1) quality factor , q = ( r 6/ r 8) ( r 2/ r 5) bandpass gain , a o = C r 2/ r 1 using the values shown in figure 25, the q range is 0.3 to 5 and the f o range is 0 to 12 khz. r8 30k w high pass output c1 1000pf c2 1000pf low pass output a2 a3 a4 a1 c3 10pf band pass output r6 10k w v in v ref a i out1 ai out1 br fb bv ref ci out1 cv ref di out1 d v ref b ad7564 i out2 ai out2 bi out2 ci out2 d dac b (r2) dac c (r3) dac d (r4) r7 30k w r5 dac a (r1) agnd notes 1. a1, a2, a3, a4, : 1/4 x ad713. 2. digital input connections are omitted. 3. c3 is a compensation capacitor to eliminate q and gain variations caused by amplifier gain and bandwidth limitations. figure 25. programmable 2nd order state variable filter
rev. a ad7564 C16C printed in u.s.a. c1977C18C10/94 mechanical information dimensions shown in inches and (mm). 28-pin dip (n-28) 28 1 15 14 0.550 (13.97) 0.530 (13.462) 1.450 (36.83) 1.440 (36.576) 0.200 (5.080) max 0.020 (0.508) 0.015 (0.381) 0.606 (15.39) 0.594 (15.09) 0.012 (0.305) 0.008 (0.203) 0.160 (4.07) 0.140 (3.56) 0.175 (4.45) 0.120 (3.05) 0.105 (2.67) 0.095 (2.41) 0.065 (1.65) 0.045 (1.14) 15 o 0 o leads are solder dipped or tin-plated alloy 42 or copper. 28-lead soic (r-28) pin 1 0.299 (7.60) 0.291 (7.39) 15 14 1 28 0.414 (10.52) 0.398 (10.10) 0.03 (0.76) 0.02 (0.51) 0.013 (0.32) 0.009 (0.23) 0.042 (1.067) 0.018 (0.457) 0.708 (18.02) 0.696 (17.67) 0.096 (2.44) 0.089 (2.26) 0.01 (0.254) 0.006 (0.15) 0.019 (0.49) 0.014 (0.35) 0.050 (1.27) bsc 1. lead no. 1 identified by a dot. 2. soic leads will be either tin plated of solder dipped in accordance with mil-m-38510 requirements. 28-lead ssop (rs-28) 1. lead no. 1 identified by a dot. 2. leads will be either tin plated or solder dipped in accordance with mil-m-38510 requirements 0.009 (0.229) 0.005 (0.127) 0.03 (0.762) 0.022 (0.558) 8 0 0.0256 (0.65) bsc 0.407 (10.34) 0.397 (10.08) 0.008 (0.203) 0.002 (0.050) 0.07 (1.78) 0.066 (1.67) pin 1 15 14 1 28 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.207)

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